This invention relates generally to row decoders used in NOR Flash memory architectures. More particularly, it relates to a semiconductor integrated circuit memory device which includes an apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages at selected wordlines and block select lines.
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "Flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such Flash EEPROMs provide electrical erasing and a small cell size. In a conventional Flash EEPROM memory device, a plurality of one-transistor core cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
One type of architecture used for Flash memories is typically referred to as a NOR Flash memory architecture which is an array of Flash EEPROM cells (floating gate devices) which are divided into a plurality of sectors. Further, the memory cells within each sector are arranged in rows of wordlines and columns of bit lines intersecting the rows of wordlines. The source region of each cell transistor within each sector is tied to a common node. Therefore, all of the cells within a particular sector can be erased simultaneously and erasure may be performed on a sector-by-sector basis. The control gates of the cell transistors are coupled to wordlines, and the drains thereof are coupled to bit lines.
In order to program the Flash EEPROM cell in conventional operation, the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example, the drain region has applied thereto a voltage V.sub.D of approximately +5.5 volts with the control gate V.sub.G having a voltage of approximately +9 volts applied thereto. These voltages produce "hot electrons" which are accelerated across the thin dielectric layer and onto the floating gate. This hot electron injection results in an increase of the floating gate threshold by approximately two to four volts.
For erasing the Flash EEPROM cell in conventional operation, a positive potential (e.g., +5 volts) is applied to the source region. The control gate is applied with a negative potential (e.g., -8 volts), and the drain region is allowed to float. A strong electric field develops between the floating gate and the source region, and a negative charge is extracted from the floating gate to the source region by way of Fowler-Nordheim tunneling.
In order to determine whether the Flash EEPROM cell has been properly programmed or not, the magnitude of the read current is measured. Typically, in the read mode of operation the source region is held at a ground potential (0 volts) and the control gate is held at a potential of about +5 volts. The drain region is held at a potential between +1 to +2 volts. Under these conditions, an unprogrammed cell (storing a logic "1") will conduct a current level approximately 50 to 100 .mu.A. The programmed cell (storing a logic "0") will have considerably less current flowing.
For example, a 64 Mb (megabit) NOR Flash memory array architecture is illustrated in FIG. 1 which consists of four vertical blocks 10, 12, 14 and 16. Each of the vertical blocks 10-16 is composed of thirty-two sectors. Each of the 128 sectors store 512 Kbits of data arranged in 256 rows of wordlines and 2048 columns of bit lines. Further, each of the sectors S0 through S127 is formed of two array blocks (FIGS. 2a and 2b) AB-1 and AB-2. A plurality of X-decoders 18 are located between the four vertical blocks 10-16 so as to decode the wordlines in each sector from the left and right sides.
Further, there is often required voltages to be internally generated that are greater than an external or off-chip power supply potential VCC which is supplied to it. For example, it is known that in Flash EEPROMs operating at VCC equal to +3.0 volts, a high voltage of approximately +4.5 volts is needed to be produced for the reading mode of operation of the memory cells. As a consequence, the semiconductor memories also generally include an internal voltage boosting circuit for generating an output signal boosted to be higher than the external supply voltage.
In FIG. 1A, there is shown a simple diagram of a conventional technique for creating a boosted voltage for a wordline. A voltage booster circuit 2 is used for generating a global wordline supply voltage VPXG at node N1, which is passed to appropriate wordlines in the various sectors S0-S127 in the four vertical blocks 10-16 of the memory array via the corresponding X-decoders 18. The global wordline supply voltage VPXG is typically in the range of +4.0 volts to +5.0 volts, which is raised above the input power supply potential VCC of a nominal +3.0 volts. This boosted voltage VPXG is a target voltage which is desired to be maintained at all of the wordlines in the various sectors during a Read mode of operation.
However, since the boosted voltage VPXG applied to the wordline is created by the booster circuit, it will vary greatly with the power supply potential VCC, process corners, and temperature. Thus, the wordline voltage will not be very accurate and will cause errors to occur during the Read operation. Further, this boosted voltage VPXG must drive both the capacitance (5 pF-8 pF) associated with the wordline loading path and the parasitic capacitance (about 30 pF) associated with the N-well loading path in the X-decoder. As a result, the boosted voltage at the selected wordline will decrease due to the high capacitive loading that must be quickly charged during the Read mode.
In view of this, there has arisen a need to provide a way of reducing the capacitive loading in Flash memory X-decoder in order to produce accurate voltage control at selected wordlines and block select lines. This is accomplished in the present invention by separating the paths to the selected-wordlines and the block select lines from the one to the N-well parasitic loading.